RESTUCCIA, FRANCESCO
RESTUCCIA, FRANCESCO
Istituto di Telecomunicazioni, Informatica e Fotonica
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Risultati 1 - 7 di 7 (tempo di esecuzione: 0.009 secondi).
ARTe: Providing real-time multitasking to Arduino
2022-01-01 Restuccia, F.; Pagani, M.; Mascitti, A.; Barrow, M.; Marinoni, M.; Biondi, A.; Buttazzo, G.; Kastner, R.
AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC
2020-01-01 Restuccia, F.; Biondi, A.; Marinoni, M.; Cicero, G.; Buttazzo, G.
Is your bus arbiter really fair? Restoring fairness in axi interconnects for FPGA SOCs
2019-01-01 Restuccia, Francesco; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G.
Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs
2020-01-01 Restuccia, F.; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G.
PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms
2022-01-01 Serra, G.; Fara, P.; Cicero, G.; Restuccia, F.; Biondi, A.
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC
2020-01-01 Restuccia, Francesco; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio
Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms
2021-01-01 Restuccia, F.; Biondi, A.
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| ARTe: Providing real-time multitasking to Arduino | 1-gen-2022 | Restuccia, F.; Pagani, M.; Mascitti, A.; Barrow, M.; Marinoni, M.; Biondi, A.; Buttazzo, G.; Kastner, R. | |
| AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC | 1-gen-2020 | Restuccia, F.; Biondi, A.; Marinoni, M.; Cicero, G.; Buttazzo, G. | |
| Is your bus arbiter really fair? Restoring fairness in axi interconnects for FPGA SOCs | 1-gen-2019 | Restuccia, Francesco; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G. | |
| Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs | 1-gen-2020 | Restuccia, F.; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G. | |
| PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms | 1-gen-2022 | Serra, G.; Fara, P.; Cicero, G.; Restuccia, F.; Biondi, A. | |
| Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC | 1-gen-2020 | Restuccia, Francesco; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio | |
| Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms | 1-gen-2021 | Restuccia, F.; Biondi, A. |