SPIRE: A 28nm Memory-Efficient Multi-Reservoir LSM Accelerator for Adaptive and Flexible Time-series Classification

Spiking Neural Networks are widely studied for their brain-inspired ability to process sequential information, yet their memory limitations often hinder the extraction of long-term dependencies. Reservoir computing, and in particular liquid state machines (LSM), has gained attention within this context for its ability to separate the recurrence and classification components into a recurrent reservoir liquid followed by a feedforward layer. However, existing LSM hardware suffers from significant design trade-offs, including large memory demands or performance degradation due to restrictive connectivity and weight precision. Inspired by these findings, we introduce SPIRE, a compact 1.13mm2 core area, fully digital multi-reservoir LSM with online learning adaptation. Implemented in TSMC 28nm CMOS technology, SPIRE is a memory-efficient multi-reservoir LSM tailored for time-series classification and edge deployment. By organizing up to eight reservoir ensembles into four parallelized cores, SPIRE enhances synaptic density and computational efficiency. Furthermore, SPIRE leverages on-the-fly generation of reservoir weights, reducing even further the memory footprint while supporting both sequential and parallelized dual operation modes. Benchmark results demonstrate that these design choices improve SPIRE’s synaptic density by up to 18.46× over prior works. SPIRE achieves 3.56 GSOPs/mm2 with just 4.91 pJ/SOP in sequential inference and up to 76.05 GSOPs/mm2 with 0.1 pJ/SOP in parallel configurations running at 55 MHz and 0.55 V.