BIONDI, ALESSANDRO
BIONDI, ALESSANDRO
Istituto di Telecomunicazioni, Informatica e Fotonica
A bandwidth reservation mechanism for axi-based hardware accelerators on FPGAs
2019-01-01 Pagani, M.; Rossi, E.; Biondi, A.; Marinoni, M.; Lipari, G.; Buttazzo, G.
A Blocking Bound for Nested FIFO Spin Locks
2017-01-01 Biondi, Alessandro; Brandenburg, Björn B.; Wieder, Alexander
A design flow for supporting component-based software development in multiprocessor real-time systems
2018-01-01 Biondi, Alessandro; Buttazzo, Giorgio; Bertogna, Marko
A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs
2017-01-01 Biondi, Alessandro; Balsini, Alessio; Pagani, Marco; Rossi, Enrico; Marinoni, Mauro; Buttazzo, Giorgio Carlo
A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling
2020-01-01 Casini, D.; Biondi, A.; Nelissen, G.; Buttazzo, G.
A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration
2022-01-01 Pagani, M.; Biondi, A.; Marinoni, M.; Molinari, L.; Lipari, G.; Buttazzo, G.
A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration
2017-01-01 Pagani, Marco; Balsini, Alessio; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio
A Multi-Domain Software Architecture for Safe and Secure Autonomous Driving
2021-01-01 Belluardo, L.; Stevanato, A.; Casini, D.; Cicero, G.; Biondi, A.; Buttazzo, G.
A Safe, Secure, and Predictable Software Architecture for Deep Learning in Safety-Critical Systems
2019-01-01 Biondi, Alessandro; Nesti, Federico; Cicero, Giorgiomaria; Casini, Daniel; Buttazzo, Giorgio Carlo
A survey of schedulability analysis techniques for rate-dependent tasks
2018-01-01 Feld, Timo; Biondi, Alessandro; Davis, Robert I.; Buttazzo, Giorgio; Slomka, Frank
Achieving Predictable Multicore Execution of Automotive Applications Using the LET Paradigm
2018-01-01 Biondi, Alessandro; DI NATALE, Marco
An I/O Virtualization Framework with I/O-Related Memory Contention Control for Real-Time Systems
2022-01-01 Borgioli, Niccolo; Zini, Matteo; Casini, Daniel; Cicero, Giorgiomaria; Biondi, Alessandro; Buttazzo, Giorgio
Analyzing Arm's MPAM From the Perspective of Time Predictability
2022-01-01 Zini, M.; Casini, D.; Biondi, A.
Analyzing parallel real-time tasks implemented with thread pools
2019-01-01 Casini, D.; Biondi, A.; Buttazzo, G.
ARTE: Arduino real-time extension for programming multitasking applications
2016-01-01 Buonocunto, Pasquale; Biondi, Alessandro; Pagani, Marco; Marinoni, Mauro; Buttazzo, Giorgio Carlo
ARTe: Providing real-time multitasking to Arduino
2022-01-01 Restuccia, F.; Pagani, M.; Mascitti, A.; Barrow, M.; Marinoni, M.; Biondi, A.; Buttazzo, G.; Kastner, R.
Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC
2021-01-01 Seyoum, Biruk; Pagani, Marco; Biondi, Alessandro; Buttazzo, Giorgio
AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC
2020-01-01 Restuccia, F.; Biondi, A.; Marinoni, M.; Cicero, G.; Buttazzo, G.
Beyond the weakly hard model: Measuring the performance cost of deadline misses
2018-01-01 Pazzaglia, Paolo; Pannocchi, Luigi; Biondi, Alessandro; DI NATALE, Marco
Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs
2023-01-01 Restuccia, Francesco; Pagani, Marco; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| A bandwidth reservation mechanism for axi-based hardware accelerators on FPGAs | 1-gen-2019 | Pagani, M.; Rossi, E.; Biondi, A.; Marinoni, M.; Lipari, G.; Buttazzo, G. | |
| A Blocking Bound for Nested FIFO Spin Locks | 1-gen-2017 | Biondi, Alessandro; Brandenburg, Björn B.; Wieder, Alexander | |
| A design flow for supporting component-based software development in multiprocessor real-time systems | 1-gen-2018 | Biondi, Alessandro; Buttazzo, Giorgio; Bertogna, Marko | |
| A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs | 1-gen-2017 | Biondi, Alessandro; Balsini, Alessio; Pagani, Marco; Rossi, Enrico; Marinoni, Mauro; Buttazzo, Giorgio Carlo | |
| A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling | 1-gen-2020 | Casini, D.; Biondi, A.; Nelissen, G.; Buttazzo, G. | |
| A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration | 1-gen-2022 | Pagani, M.; Biondi, A.; Marinoni, M.; Molinari, L.; Lipari, G.; Buttazzo, G. | |
| A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration | 1-gen-2017 | Pagani, Marco; Balsini, Alessio; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio | |
| A Multi-Domain Software Architecture for Safe and Secure Autonomous Driving | 1-gen-2021 | Belluardo, L.; Stevanato, A.; Casini, D.; Cicero, G.; Biondi, A.; Buttazzo, G. | |
| A Safe, Secure, and Predictable Software Architecture for Deep Learning in Safety-Critical Systems | 1-gen-2019 | Biondi, Alessandro; Nesti, Federico; Cicero, Giorgiomaria; Casini, Daniel; Buttazzo, Giorgio Carlo | |
| A survey of schedulability analysis techniques for rate-dependent tasks | 1-gen-2018 | Feld, Timo; Biondi, Alessandro; Davis, Robert I.; Buttazzo, Giorgio; Slomka, Frank | |
| Achieving Predictable Multicore Execution of Automotive Applications Using the LET Paradigm | 1-gen-2018 | Biondi, Alessandro; DI NATALE, Marco | |
| An I/O Virtualization Framework with I/O-Related Memory Contention Control for Real-Time Systems | 1-gen-2022 | Borgioli, Niccolo; Zini, Matteo; Casini, Daniel; Cicero, Giorgiomaria; Biondi, Alessandro; Buttazzo, Giorgio | |
| Analyzing Arm's MPAM From the Perspective of Time Predictability | 1-gen-2022 | Zini, M.; Casini, D.; Biondi, A. | |
| Analyzing parallel real-time tasks implemented with thread pools | 1-gen-2019 | Casini, D.; Biondi, A.; Buttazzo, G. | |
| ARTE: Arduino real-time extension for programming multitasking applications | 1-gen-2016 | Buonocunto, Pasquale; Biondi, Alessandro; Pagani, Marco; Marinoni, Mauro; Buttazzo, Giorgio Carlo | |
| ARTe: Providing real-time multitasking to Arduino | 1-gen-2022 | Restuccia, F.; Pagani, M.; Mascitti, A.; Barrow, M.; Marinoni, M.; Biondi, A.; Buttazzo, G.; Kastner, R. | |
| Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC | 1-gen-2021 | Seyoum, Biruk; Pagani, Marco; Biondi, Alessandro; Buttazzo, Giorgio | |
| AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC | 1-gen-2020 | Restuccia, F.; Biondi, A.; Marinoni, M.; Cicero, G.; Buttazzo, G. | |
| Beyond the weakly hard model: Measuring the performance cost of deadline misses | 1-gen-2018 | Pazzaglia, Paolo; Pannocchi, Luigi; Biondi, Alessandro; DI NATALE, Marco | |
| Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs | 1-gen-2023 | Restuccia, Francesco; Pagani, Marco; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio |