This paper [3] tackles the problem of optimal placement of complex real-time embedded applications on heterogeneous platforms [7]. Applications are composed of directed acyclic graphs (DAGs) of tasks, with each DAG having a minimum inter-arrival period for its activation requests, and an end-to-end deadline within which all of the computations need to terminate since each activation. The platforms of interest are heterogeneous power-aware multicore platforms with DVFS capabilities, including big.LITTLE Arm architectures, and platforms with GPU or FPGA hardware accelerators with Dynamic Partial Reconfiguration capabilities. Tasks can be deployed on CPUs using partitioned EDF-based scheduling. Additionally, some of the tasks may have an alternate implementation available for one of the accelerators on the target platform, which are assumed to serve requests in non-preemptive FIFO order. The system can be optimized by: minimizing the average power consumption, respecting precise timing constraints; maximizing the minimum relative slack among all deployed DAG applications, respecting given power consumption constraints; or even a combination of these, in a multi-objective formulation, obtaining a minimum-power and robust deployment, as demonstrated by the obtained experimental results.
Multi-Criteria Optimization of Real-Time DAGs on Heterogeneous Platforms under P-EDF
Cucinotta, Tommaso
;Amory, Alexandre;Ara, Gabriele;Paladino, Francesco;Di Natale, Marco
2025-01-01
Abstract
This paper [3] tackles the problem of optimal placement of complex real-time embedded applications on heterogeneous platforms [7]. Applications are composed of directed acyclic graphs (DAGs) of tasks, with each DAG having a minimum inter-arrival period for its activation requests, and an end-to-end deadline within which all of the computations need to terminate since each activation. The platforms of interest are heterogeneous power-aware multicore platforms with DVFS capabilities, including big.LITTLE Arm architectures, and platforms with GPU or FPGA hardware accelerators with Dynamic Partial Reconfiguration capabilities. Tasks can be deployed on CPUs using partitioned EDF-based scheduling. Additionally, some of the tasks may have an alternate implementation available for one of the accelerators on the target platform, which are assumed to serve requests in non-preemptive FIFO order. The system can be optimized by: minimizing the average power consumption, respecting precise timing constraints; maximizing the minimum relative slack among all deployed DAG applications, respecting given power consumption constraints; or even a combination of these, in a multi-objective formulation, obtaining a minimum-power and robust deployment, as demonstrated by the obtained experimental results.| File | Dimensione | Formato | |
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