Scalable Low-Power Hardware Architecture for Spike-Timing-Dependent SNN Learning Algorithms

On-line learning algorithms used for spiking neural networks (SNNs) tend to rely on the exact timing between pre/postsynaptic spikes to compute updates on synaptic weights. Some traditional approaches implement a series of counters and lookup tables to compute weight updates based on the timing between spikes. Although relatively simple, these approaches scale poorly with large networks, increasing the number of active counters and redundant accesses to the look-up tables (LUTs), incurring large area overheads and power inefficiencies during training phases. We propose a hardware (HW) architecture synthesized in CMOS 28 nm technology that eliminates all these redundant accesses and improves the efficiency for large SNNs, paving the way for spike-time-based learning algorithms. The results show that the proposed approach reduces the reading power of the LUT up to 70% compared to the traditional approaches, with a reduction in power scaling with larger networks. In addition, only the hardware circuitry shows a reduction in power from 1.3 × to 1.74 × in networks composed of 2 5 6 to 1 0 2 4 neurons.